A power loss test could be one of the tests that a manufactured chip or integrated circuit (IC) is required to pass when the chip is being evaluated on an assembly line or in a laboratory. For example, a mobile phone that runs on batteries may undergo such test. When a chip experiences a sudden power loss from an internal or external power supply, the power level may decrease gradually to a certain level but not all the way to zero such that a power on reset (POR) may not be triggered to generate a reset signal to reset the power supply circuit of a chip. If the POR is not triggered to reset the chip, memory elements could be in an unknown state.
As seen from FIG. 1, after a POR 101 has been triggered, the power supply of a chip may go from 0 volt to VCC, a normal bias voltage. However, suppose that the power supply of the chip suddenly drops as shown in the power loss area 102, the memory elements of the chip may enter an unknown state if the power supply drops to a voltage that is below a minimum threshold but not quite reaching about 0 volt to trigger a POR as shown in the dead zone area 103. The dead zone area 103 refers to the range of power supply voltage within which the memory elements would not be guaranteed to keep their recorded states but at the same time a POR would not be triggered.
The reason that the chip would likely be in an unknown state is due to memory elements losing their recorded states loss when power supply level drops too low. When power supply level drops to the dead zone area 103, memory elements such as flip flops, latches, and so forth may not be able to keep their recorded states and thus causing the chip to enter into an unknown state. After the chip entering into an unknown state, the chip would likely malfunction since the state machine would be unable to proceed to the intended states. Therefore, a chip entering into an unknown state caused by the power supplying entering into the dead zone area 103 could be an issue that needs to be addressed.